1. Field of the Invention
The invention relates to methods of fabricating semiconductor devices, including integrated circuits, and more particularly, to a method of forming isolated structures and interconnections in an integrated circuit and to isolated and interconnected structures.
2. Background of the Invention
Integrated circuits generally require electrical isolation between devices fabricated on the same piece of semiconductor. Isolation structures are necessary to prevent the establishment of parasitic channels between adjacent devices. A variety of techniques have been developed to isolate devices in integrated circuits. Two common techniques are Local Oxidation of Silicon ("LOCOS") and trench isolation. LOCOS involves the formation of a semi-recessed oxide in the non-active or field areas of the substrate. Trench isolation involves the formation of an oxide in a trench created in the non-active or field areas of the substrate.
In LOCOS isolation, the oxide is selectively grown over the desired field regions. This is done by covering the active regions with a thin layer of silicon nitride that prevents oxidation from occurring beneath them. After the nitride layer has been etched away in the field regions, the silicon in those regions may be etched for fully-recessed LOCOS or more commonly is simply oxidized without etching to form a semi-recessed LOCOS. Metal interconnects between devices overlie the field oxide regions, wherein the field oxide regions (and optional channel stop implants) prevent the interconnects from forming gates of parasitic MOS transistors. The conductive material that is, for example, the gate portion of the device also overlies a portion of the field oxide region to maintain the field effect of the device. In 0.5 .mu.m technology, the overlap typically approximates 1/4 .mu.m on each side of the active region. This overlap translates to increased spacing requirements for individual devices in an integrated circuit. Other problems associated with conventional semi-recessed LOCOS include, bird's beak structures of field oxide encroaching into the device-active region, inadequate planarity of the surface topography for submicron lithography needs, and inadequate field oxide thickness in submicron regions.
FIG. 1 shows a planar top view of a prior art LOCOS structure. FIG. 1 is a semi-recessed LOCOS structure with thick field oxide areas surrounding the active area. A metal interconnect overlies the active region of the structure and extends over the field oxide regions. FIG. 2 is a planar side view of the prior art semi-recessed LOCOS structure taken through line A--A of FIG. 1. FIG. 2 shows the thick field oxide regions surrounding the active region.
FIG. 3 demonstrates the consequence wherein the conductive material that makes up the field effect transistor does not completely overlie the active region. In FIG. 3, the field effect of the active device region is diminished because the conductor material does not extend completely through the active region. In this situation, the conductive layer (e.g., polysilicon) cannot control the flow of electricity through the channel.
Trench technology involves the placing of an isolation trench in the non-active or field oxide regions of the integrated circuit to isolate individual devices. Typically a trench isolation method proceeds by masking an active region and exposing a field region and etching a trench in the exposed semiconductor in the field region. Next, a passivation oxide is grown on the side walls of the trench. The passivation growth ties up loose bonds that have been exposed when the trench is made. Once a layer of passivation oxide is formed on the side walls of the trench, the trench is filled with atmospheric-CVD polysilicon, LPCVD polysilicon, CVD SiO.sub.2. After refill, the trench is planarized with the substrate by an etch-back process. Next, active devices are formed in the active region, wherein such active regions are surrounded by the isolation trench.
The conventional trench depth falls into three categories: shallow trenches (&lt;1 .mu.m), moderate depth trenches (1-3 .mu.m), and deep, narrow trenches (&gt;3 .mu.m deep, &lt;2 .mu.m wide). Shallow trenches are used for isolating devices of the same type, but often suffer from problems with preventing latchup and isolating N-channel from P-channel devices in CMOS. Moderate depth trenches are therefore used for bipolar integrated circuits and to prevent latchup in CMOS. Deep, narrow trench structures have been utilized to prevent latchup and to isolate N-channel from P-channel devices in CMOS circuits, and to isolate transistors of bipolar circuits, and to serve as storage-capacitor structures in DRAMs. Thus, there are many differing trench depths for differing applications. For example, if an epitaxial layer is used to change the doping of the semiconductor substrate so that there is a lightly doped region above a heavily doped region, the trench depth need only extend through the lightly doped region and into the heavily doped region to prevent parasitic conductance. Another example is silicon-on-insulator applications where, for capacitance reasons, the trench depth extends all the way through the silicon layer, which is typically approximately 0.25 .mu.m thick.
The problems associated with the conventional trench isolation technique are that the physical shape of the structure (i.e., abrupt gate to trench transition) can induce high electric field concentrations adjacent to the trench. Further, care must be taken to assure that the subsequent conductive layer extends all the way across the active region so as to avoid the problem of maintaining the field effect of the device. There is no way to know for certain that the conductive layer of the transistor extends completely across the active area without overlapping the conductive layer onto the isolation trench.
The etch-back process to planarize the trench with the semiconductor substrate must also be carefully monitored to avoid removing the isolation material in the trench Further, in refilling trenches of differing widths, a substantial amount of refill material must be used to ensure that all the trenches are completely filled. The excess refill material is difficult to etch and difficult to control.
FIGS. 4-13(b) demonstrate the prior art trench isolation technique process. First, a masking layer 12 is applied over a semiconductor substrate to expose a trench region. Next, a trench 14 is etched into the semiconductor substrate 10. Next, a passivation oxide 16 is grown on the side walls of the trench 14. The trench is then filled with a refill material 18. Next, the device is planarized to remove excess refill material. The masking layer 12 is then removed, as shown in FIG. 9, and the passivation layer is grown over the refill material. FIG. 10 shows a gate oxide 20 grown in the device region of the substrate 10. FIG. 11 shows the deposition of a polysilicon layer 22 over the gate oxide 20 in the active region. FIG. 12 shows the formation of a gate of polysilicon 22 overlying a gate oxide 20. FIG. 12 also shows the formation of a source/drain diffusion region 24 in the semiconductor substrate.
FIG. 13(a) shows a planar top view of a trench-isolated device region wherein a trench 16 surrounds a conductive layer (e.g., polysilicon layer) 22 and source/drain diffusion regions 24. In FIG. 13(a), the conductive layer 22 overlies the trench 16 to ensure that the conductive material extends completely over the active area. As noted above, this is necessary to ensure the field effect of the transistor. FIG. 13(b) is a planar side view of the structure in FIG. 13 drawn through line A--A. FIG. 13(b) shows adjacent isolated active-device regions wherein the conductive material of each active device overlaps the trench. The overlapping further requires that the trench be wide enough to accommodate for the edge placement accuracy of the conductive layer deposition and the minimum feature size.
Thus far, the discussion has focused on isolating active-device regions within the single-crystal semiconductor substrate of an integrated circuit. Isolating active device regions is extremely important in integrated circuits. These individual devices are linked to form simple structures like inverters or more complex structures like DRAMs and SRAMs. The technology used to connect these isolated devices through specific electrical paths involves thin film paths fabricated above a dielectric (e.g., SiO.sub.2) that covers the active-device structures. Wherever a connection is needed between a conductor film and the underlying conductive layer (e.g., polysilicon layer), an opening in the dielectric must be provided to allow such interconnects/contacts to occur. FIG. 14(a) illustrates a planar side view of a CMOS inverter circuit. FIG. 14(b) illustrates the circuit schematic for the device of FIG. 14(a). In the inverter circuit, the drains of the two transistors are connected together by conductor film 26 and form the output, while the input terminal is the common connection 27 to the transistor gates. In a structure such as the inverter shown, the metallization is done simultaneously. In other words, the openings or via for the metallization to the drains and to the gates are made together then a metal (e.g., Al) is deposited in the appropriate opening. Another alternative commonly employed is to create the adjacent gate structures of a single layer of polysilicon that bridges the isolation trench and any other insulating layers to insulate the diffusion regions of the adjacent devices from the common gate.
The same procedure is used to create six transistor static random access memory (6T SRAM) structures. The 6T SRAM structure is comprised of a pair of cross-coupled inverters that store a bit state. Like the simple inverter process, the metallization of the 6T SRAM structure is generally accomplished with the steps of creating vias and depositing a metal (e.g., Al) in a single step or a series of steps to create, for example, the inverter structures and the bit and word lines.
FIG. 15(a) illustrates a top view of a 6T SRAM structure with trench isolation. FIG. 15(b) illustrates a schematic of a 6T SRAM CMOS structure. FIG. 15(a) shows four polysilicon lines 29 formed into gates. An isolation trench 30 runs horizontally through the structure illustrated in FIG. 15(a). Several contact openings 28 are formed in the structure to create the inverters, the bit and word lines, and the V.sub.SS power line and the low-resistance V.sub.CC line. The contacts 28 are formed with rectangular masks openings with the resulting contact via forming circular openings. The design rules currently used for the CMOS SRAM structure require that the mask that is used to create the contact openings be placed sufficiently far away from other contact openings to hold off voltage leakage. With 0.5 micron technology, a lens typically prints contact openings no closer than 0.5 microns to one another, as a general rule, to compensate for the resolution of the lens and avoid bridging of contacts. FIG. 15(a) illustrates the separation 31 between adjacent mask openings. FIG. 15(c) illustrates adjacent contact openings spaced less than the required distance from one another. FIG. 15(c) illustrates the bridging 100 between the adjacent contacts 28. Thus, the minimum size of the SRAM device is limited by the required distance of separation between adjacent mask openings.